Read Only Memory (ROM) is used in various devices ranging from calculators to mainframe computer systems. Normally, ROM is used to store critical instructions or data for use by a processor. An example of such instructions would be system boot up instructions. The processor can access these instructions or data by supplying an address to the memory. The instructions are then supplied by the memory to the processor for execution.
FIG. 1 is a block diagram illustrating a typical block of ROM. Here, the block of ROM 100 is divided into three segments 101, 102 and 103. Each of these segments may represent a range of addresses. For example, segment 101 may represent addresses from 0 to 255, segment 102 may represent addresses 256 to 511, and segment 103 may represent addresses 512 to 767. The block of ROM 100 is accessed through an address bus 104. Data is then read from the appropriate address in the ROM and output on the data bus 105.
FIG. 2 is a simplified schematic illustrating the details of a ROM design and the implementation of a prior art sensing gate and latch. A typical ROM circuit consists of an address detection gate 201 connected to each word-line 205. Typically, a word-line such as word-line 205 will contain a number of bit-lines 203 and 207. Further, memory contains a number of word-lines such as illustrated here by word-lines 205, 206, and 208. Each bit-line is connected to a gate 209 which in turn drives an output 210.
A decoded address is provided on address lines 200. This address is detected by a gate 201 attached to a word-line. If the word-line is selected, the selected cell 202 will then be discharged. The discharge of this bit-line 203 will then be passed through a gate 209 to the output 210. In the prior art, this output 210 may then applied to a sensing gate 211. In some applications this sensing gate may have more than one bit-line applied to the inputs such as 210 and 213. If the output of this sensing gate 211 is required to remain on for more than a single clock cycle, it could be latched by an external latch 212.
Normally, an address is supplied to a ROM and data from that address must be supplied within one clock cycle. As processor speed increases, the time in which a ROM must supply data decreases. Several solutions have been provided to address this problem. One solution was to divide one bit-line into two. This method reduced the capacitance of the individual lines allowing for quicker discharge of the cell. This discharge could then be latched by an external latch to prolong the signal through an entire clock cycle. However, this external latch increased circuit complexity and slowed down overall response times. As processor speeds increase, this solution becomes less effective.